vishay siliconix sip41103 document number: 72718 s- 61692 ?rev. e, 04 -sep-06 www.vishay.com 1 synchronous rectification n-channel mosfet driver for dc/dc conversion features ? 5 v gate drive ? undervoltage lockout ? internal bootstrap diode ? adaptive shoot-through protection ? synchronous mosfet disable ? adjustable highside propagation delay ? switching frequency up to 1 mhz ? drive mosfets in 4.5 to 50 v systems applications ? multi-phase dc/dc conversion ? high current synchronous buck converters ? high frequency synchronous buck converters ? asynchronous-to-synchronous adaptations ? mobile computer dc/dc converters ? desktop computer dc/dc converters description sip41103 is a high-speed synchronous rectification mosfet driver with adaptive shoot-through protec- tion for use in high frequency, high-current, mul- tiphase dc-dc synchronous rectifier buck converter. it is designed to operate at the switching frequencies up to 1 mhz. the high-side driver is bootstrapped to allow driving n-channel mosfet. adaptive shoot- through protection prevents simultaneous conduction of external mosfets. adding a capacitor to the delay pin can further increase the high-side driver turn-on delay by 1.2 ns/pf for further shoot-through protec- tion. the sip41103 is available in both standard and lead (pb)-free 10-pin mlp33 packages and is specified to operate over the industrial temperature range of - 40 c to 85 c. typical application circuit *pb containing terminations are not rohs compliant, exemptions may apply + 5 to 50 v + 5 v gnd controller gnd pwm en sync out l lx v dd boot delay sip41103 1 f 10 pf v out 0.1 f gnd out h available pb-free rohs* compliant
www.vishay.com 2 document number: 72718 s-61692?rev. e, 04-sep -06 vishay siliconix sip41103 notes: a. device mounted with all leads soldered or welded to pc board b. derate 9.6 mw/c stresses beyond those listed under "absol ute maximum ratings" may cause permanent dam age to the device. these are stress rating s only, and functional operation of the device at t hese or any other conditions beyond those indi cated in the operational sections of t he specifications is not implied. exposure to absolute maximum rating/condi tions for extended periods may affect device reliability. absolute maximum ratings (all voltages referenced to gnd = 0 v) parameter limit unit v dd , pwm, en sync , delay 7 v lx, boot 55 boot to lx 7 storage temperature - 40 to 150 c operating junction temperature 125 power dissipation a,b mlp-33 960 mw thermal impedance( ja ) a,b 105 c/w recommended operating range (all voltages refere nced to gnd = 0 v) parameter limit unit v dd 4.5 to 5.5 v v boot 4.5 to 50 c boot 100 nf to 1 f operating temperature range - 40 to 85 c specifications a parameter symbol test conditions unless specified v dd = 5 v, v boot - v lx = 5 v, c load = 3 nf t a = - 40 to 85 c limits unit min a typ b max a power supplies supply voltage v dd 4.5 5.5 v quiescent current i ddq f pwm = 1 mhz, c load = 0 2.3 3.0 ma shutdown current i sd1 pwm = 0 v 1 a i sd2 pwm = 5 v 30 60 reference voltage break-before-make v bbm lx falling 1 v pwm input input high v ih 4.0 v dd v input low v il 0.5 bias current i b 0.3 1 a en sync inputs input high v ih 2.0 v dd v input low v il 1.0 bias current i b 1 a high-side undervoltage lockout threshold v uvhs rising or falling 2.5 3.35 3.75 v bootstrap diode forward voltage v f i f = 10 ma, t a = 25 c 0.7 0.76 0.82 v
document number: 72718 s- 61692 ?rev. e, 04 -sep-06 www.vishay.com 3 vishay siliconix sip41103 notes: a. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum (- 40 to 85 c). b. typical values are for design ai d only, not guaranteed nor subject to production testing and are measured at v cc = 5 v unless otherwise noted. c. guaranteed by design. parameter symbol test conditions unless specified v dd = 5 v, v boot - v lx = 5 v, c load = 3 nf t a = - 40 to 85 c limits unit min a typ b max a mosfet drivers high-side drive current c i pkh(source) 0.9 a i pkh(sink) 1.1 low-side drive current c i pkl(source) 0.8 i pkl(sink) 1.5 high-side driver impedance r dh(source) 2.5 3.8 r dh(sink) 2.2 3.3 low-side driver impedance r dl(source) 3.4 5.1 r dl(sink) 1.4 2.1 high-side rise time t rh 10 % - 90 % 32 40 ns high-side fall time t fh 90 % - 10 % 36 45 high-side propagation delay c t d(off)h see timing waveforms 20 t d(on)h see timing waveforms 30 low-side rise time t rl 10 % - 90 % 45 55 low-side fall time t fl 90 % - 10 % 20 30 low-side propagation delay c t d(off)l see timing waveforms 30 t d(on)l see timing waveforms 30 lx timer lx falling timeout c t lx 420 ns v dd undervoltage lockout threshold rising v uvlor 4.3 4.5 v threshold falling v uvlof 3.7 4.1 hysteresis 0.4 power on reset time c 2.5 ms thermal shutdown temperature t sd temperature rising 165 c hysteresis t h temperature falling 25 specifications a
www.vishay.com 4 document number: 72718 s-61692?rev. e, 04-sep -06 vishay siliconix sip41103 timing waveforms pin configuration and truth table note: a. after the device is enabled. t d(on)l t d(off)h t d(off)l pwm out h out l t d(on)h 10 % 90 % 50 % 90 % 10 % 10 % 10 % 50 % 90 % 90 % t fl t rh t rl t fh 1 v lx 2 3 4 10 9 8 7 out h boot pwm delay lx en sync nc v dd top view 5 gnd 6 out l mlp33 truth table a pwm en sync out h out l llll lhlh hxhl ordering information standard part number lead (pb)-free part number temperature range marking SIP41103DM-T1 SIP41103DM-T1-e3 - 40 to 85 c 41a3 eval kit temperature range sip41103db - 40 to 85 c pin description pin number name function 1 out h high-side mosfet gate drive 2 boot bootstrap supply for high-side driver. a capacitor connects between boot and lx 3 pwm input signal for the mosfet drivers 4 delay connection for the highside d ealy adjustment capacitors 5 gnd ground 6 out l synchronous or low-side mosfet gate drive 7 v dd + 5 v supply 8 nc no connect 9 en sync enables out l , the driver for the synchronous mosfet 10 lx connection for source of high-side mosfet, dr ain of the low-side mosfet and the inductor
document number: 72718 s-61692 ?rev. e, 04-sep-06 www.vishay.com 5 vishay siliconix sip41103 functional block diagram detailed operation pwm the pwm pin controls the switching of the external mosfets. the driver logic operates in a noninverting configuration. the pwm input stage should be driven by a signal with fast transition times, like those pro- vided by a pwm controller or logic gate, (< 200 ns). the pwm input functions as a logic input and is not intended for applications where a slow changing input voltage is used to generate a switching output when the input switching threshold voltage is reached. enable the device is enabled by edge sensing of transitions on pwm, high or low. a minimum pwm frequency of 2 khz is required to keep the device enabled. when continuous pwm transitions are present, and after power-on reset time has elapsed, out h and out l will become active. low-side driver the supplies for the low-side driver are v dd and gnd. during shutdown, out l is held low. high-side driver the high-side driver is isolated from the substrate to create a floating high-side driver so that an n-channel mosfet can be used for the high-side switch. the supplies for the high-side driver are boot and lx. the voltage is supplied by a floating bootstrap capaci- tor, which is continually recharged by the switching action of the output. during shutdown out h is held low. bootstrap circuit the internal bootstrap diode and a bootstrap capacitor form a charge pump that supplies voltage to the boot pin. an integrated bootstrap diode replaces the exter- nal schottky diode and bootstrap only a capacitor is necessary to complete the circuit. the bootstrap capacitor is sized according to. where q gate is the gate charge needed to turn on the high-side mosfet and v boot-lx is the amount of droop allowed in the bootstrap supply voltage when the high-side mosfet is driven high. the bootstrap capacitor value is typically 0.1 f to 1 f. the boot- strap capacitor voltage rating must be greater than v dd + 5 v to withstand transient spikes and ringing. shoot-through protection the external mosfets are prevented from conduct- ing at the same time during transitions. break-before- make circuits monitor the voltages on the lx pin and the out l pin and control the switching as follows: when the signal on pwm goes low, out h will go low after an internal propagation delay. after the voltage figure 1. pwm gnd v dd out h lx out l otp v dd boot v bbm ? + uvlo delay en sync delay c boot = (q gate / v boot- lx ) x 10
www.vishay.com 6 document number: 72718 s-61692?rev. e, 04-sep -06 vishay siliconix sip41103 on lx falls below 1 v by the inductor action, the low- side driver is enabled and out l goes high after some delay. when the signal on pwm goes high, out l will go low after an internal propagation delay. after the voltage on out l drops below 1 v the high-side driver is enabled out h will go high after an internal propaga- tion delay. if lx does not drop below 1 v within 400 ns after out h goes low, out l is forced high until the next pwm transition. delay the addition of a capacitor between delay and gnd will increase the propagat ion delay time for out h going high. delay capacitance may be added to pre- vent shoot-through current in the low-side mosfet due to the finite time between out l going low and the continuing conduction of the low-side mosfet. choose a mosfet with lower gate resistance to reduce this effect. if necessary, choose a capacitor value that prevents mosfet conduction under worst- case temperature and manufacturing conditions. prop- agation delay is increased according to the ratio of 1.2 ns/pf. synchronous mosfet enable under light load conditions, efficiency can be increased by disabling the synchronous mosfet, thus avoiding the gate charge losses of the synchro- nous mosfet. when en sync is low, out l is forced low. when high, the low-side driver operates normally. en sync should be driven by a 5-v signal. shutdown the driver enters shutdown mode when a period of inactivity on pwm elapses. shutdown current is less than 1 a. v dd bypass capacitor mosfet drivers draw large peak currents from the supplies when they switch. a local bypass capacitor is required to supply this current and reduce power sup- ply noise. connect a 1 f ceramic capacitor as close as practical between the v dd and gnd pins. undervoltage lockout undervoltage lockout prevents control of the circuit until the supply voltages reach valid operating levels. the uvlo circuit forces out l and out h to low when v dd is below its specified voltage. a separate uvlo forces out h low when the voltage between boot and lx is below the specified voltage. thermal protection if the temperature rises above 165 c, the thermal pro- tection disables the drivers. the drivers are re-enabled after the temperature has decreased below 140 c. typical characteristics i dd vs. c load vs. frequency 0 10 20 30 40 50 012345 c load (nf) 1 mhz i d d ) a m ( 500 khz 200 khz high side turn on delay vs. c delay 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 0 102030405060708090100110 c delay (pf) t ) n o ( d h ) s n (
vishay siliconix sip41103 document number: 72718 s-61692 ?rev. e, 04-sep-06 www.vishay.com 7 typical waveforms vishay siliconix maintains worldwide manufac turing capability. products ma y be manufactured at one of several qualified locatio ns. reliability data for silicon tech- nology and package reliability represent a composite of all qua lified locations. for related documents such as package/tape dra wings, part marking, and reliability data, see http://www.vishay.com/ppg?72718 figure 4. pwm signal vs. hs gate and ls gate (rising) figure. 6 en sync delay 50 ns/div pwm in 2 v/div v lx 2 v/div 50 ns/div pwm in 5 v/div hs gate 5 v/div ls gate 5 v/div 50 s/div hs gate 5 v/div ls gate 5 v/div en sync 5 v/div figure 5. pwm signal vs. hs gate and ls gate (falling) 50 ns/div pwm in 2 v/div v lx 2 v/div 50 ns/div pwm in 5 v/div hs gate 5 v/div ls gate 5 v/div
document number: 91000 www.vishay.com revision: 18-jul-08 1 disclaimer legal disclaimer notice vishay all product specifications and data are subject to change without notice. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, ?vishay?), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. vishay disclaims any and all li ability arising out of the use or application of any product describ ed herein or of any information provided herein to the maximum extent permit ted by law. the product specifications do not expand or otherwise modify vishay?s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of vishay. the products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. customers using or selling vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify vishay for any damages arising or resulting from such use or sale. please contact authorized vishay personnel to obtain written terms and conditions regarding products designed for such applications. product names and markings noted herein may be trademarks of their respective owners.
|
